Coverage has become a key technology in the pursuit of efficient and accurate verification of large designs. Obviously, simulation is still the cornerstone of verification, but the time when a single ...
With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate ...
The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
Some results have been hidden because they may be inaccessible to you
Show inaccessible results