Nasdaq

GBT’s Automatic Generation of Integrated Circuits Layout Blocks (IP) Patent, Received a Notice of Allowance, Expected To Be Granted In The Next Upcoming Months

SAN DIEGO, May 16, 2023 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) (“GBT” or the “Company”), received a notice of allowance from the United States Patent and Trademark Office with ...
Nasdaq

GBT is Developing an EDA Technology For Automatic Generation of Integrated Circuits Layout IPs

SAN DIEGO, Sept. 28, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), is developing EDA (Electronic Design Automation) software technology to automate the ...
Business Wire

Silicon Topology Joins TSMC Design Center Alliance (DCA)

HSINCHU, Taiwan--(BUSINESS WIRE)--Silicon Topology, a Taiwan-based leading ASIC/SoC physical layout design service provider, today announced that it has joined the Design Center Alliance (DCA) of TSMC ...
Electronic Design

How to Design a Chip for Under $1,000 (Part 1): Book Recommendations

In the first of a multi-part series on how to design a custom chip for under $1,000, our Analog Editor gets you started with a Magnificent 7 list of textbooks. TinyTapeout offers a course that ...
EDN

Taking the Guesswork Out of DDR Design with Integrated Schematic, Layout and Simulation Tools

DDR memory is quickly becoming not only the leading technology but the only technology used in memory design. As such, DDR systems are in high demand in the tech industry. High-speed simulation tools ...