EDN

Building a better memory controller: architectural performance exploration of an AXI memory controller

Communicationbetween processors and memories is often a major bottleneck, making the designof the memory controller a critical task in determining overall system-levelperformance. The memory ...
Hosted on MSN

How your memory controller could be a hidden bottleneck in your PC

If you’re an enthusiast trying to get the most performance out of your RAM kit, you might find yourself spending hours tuning for higher frequencies or tighter timings. What you may find, on some ...
Design-Reuse

Design Considerations for High Bandwidth Memory Controller

High Bandwidth Memory (HBM) is a high-performance 3D-stacked DRAM. It is a technology which stacks up DRAM chips (memory die) vertically on a high speed logic layer which are connected by vertical ...
EDN

DDR3 memory interface controller IP speeds data processing applications

DDR3 memory systems can provide a significant performance boost to a variety of data processing applications. However, compared to previous generations (DDR and DDR2), DDR3 memory devices have some ...
Design-Reuse

A Performance Architecture Exploration and Analysis Platform for Memory Sub-systems

The memory-subsystem includes a memory device such as DRAM, memory controller and physical/IO layer (PHY). There are several parameters that affect the performance of the memory subsystem, including ...