To test complex devices, test engineers must rely on the vector sets generated by verification engineers. Unfortunately, verification engineers—who work in a software simulation environment—often have ...

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Functional verification is nearing an inflection point, brought on by rising complexity and the many tentacles that are intermixing it with other disciplines. New abstractions or different ways to ...

BENGALURU, India — Two engineers at Oski Technology Inc. (Fremont, Calif.) have demonstrated a formal verification planning process and associated verification strategy that they say is a ...

The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much from between 50-70% of the entire ...

Enthusiast and frequent leak-spotter Gray (@Olrak29_ on Xwitter) spied a fresh job posting from Intel that's got the tight-knit community of hardware nerds buzzing with speculation on Chipzilla's ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...

Apple is helping to promote a new Design Verification Engineering training course designed to help graduates get jobs at Israeli tech firms and startups, by hosting a meetup for course candidates at ...

It appears that Intel could be making plans to ditch its current hybrid core design, and return to a Unified Core Design for ...